1. Field of the Invention
The present invention relates to a program circuit capable of recording data in a non-volatile manner and a configuration of a semiconductor memory device using the same program circuit. More particularly, the present invention relates to a program circuit that is applied to a semiconductor memory device including a redundant circuit and a configuration of a semiconductor memory device having such a program circuit.
2. Description of the Background Art
FIG. 17 is a block diagram showing a configuration of a main portion of a conventional semiconductor memory device that includes a redundant circuit.
A memory cell array 1 includes a plurality of word lines WL, a plurality of bit line pairs BL crossing the plurality of word lines WL, and a plurality of memory cells MC provided at the respective crossing points of word lines WL and bit line pairs BL. Memory cell array 1 further includes a redundant word line RWL and a plurality of memory cells MC connected to the redundant word line RWL.
A decoder 2 and a sense amplifier unit 13 are connected to memory cell array 1. Sense amplifier unit 13 includes a plurality of sense amplifiers connected to the plurality of bit line pairs BL, a plurality of transfer gates, and a decoder.
This semiconductor memory device is provided with a replacement circuit 10. Replacement circuit 10 includes a redundancy select circuit 3, a replacement address program circuit 4 and a NAND circuit 5. Replacement circuit 10 and redundant word line RWL constitute a redundancy circuit.
An operation of the semiconductor memory device shown in FIG. 17 will now be described.
Decoder 2 responds to an X address signal XA and selects one of the plurality of word lines WL within memory cell array 1, and raises the potential of the selected word line WL to an H level. Thus, data are read out from memory cells MC connected to the selected word line WL to corresponding bit line pairs BL. The data thus read out are amplified by the sense amplifiers provided in sense amplifier unit 13. The decoder in sense amplifier unit 13 responds to a Y address signal YA and renders one of the plurality of transfer gates conductive. As a result, one piece of data is output.
If there is a defect associated with a certain word line WL, redundant word line RWL is used instead of that word line WL. In this case, the output of redundancy select circuit 3 attains an H level. An address of the word line WL to be replaced is programmed in replacement address program circuit 4.
If an address designated by X address signal XA matches the address (replacement address) programmed in replacement address program circuit 4, then the output of replacement address program circuit 4 attains an H level. When the outputs of redundancy select circuit 3 and replacement address program circuit 4 both attain an H level, the output of NAND circuit 5 (a decoder inactivation signal DA) attains an L level. Thus, the decoder becomes inactive, and all the word lines WL enter an unselected state. The potential of redundant word line RWL rises to an H level.
Thus, in response to a defective word line WL or a word line WL connected to a defective memory cell MC having been selected, redundant word line RWL is selected instead of the word line WL.
Although not shown in FIG. 17, memory cell array 1 may include a redundant bit line pair.
FIG. 18 is a circuit diagram illustrating a configuration of a fuse program circuit 810 included in redundancy select circuit 3.
Referring to FIG. 18, fuse program circuit 810 includes a fuse element F1 provided between a node N1 and a power supply potential Vcc; a MOS capacitor C1 provided between node NI and a ground potential GND; an N channel MOS transistor QN1 provided between node N1 and a ground potential GND; and an inverter INV1 that receives and inverts the potential of node N1 and supplies its output to a gate of transistor QN1.
The potential at an output node N2 of inverter INV1 becomes an output level of fuse program circuit 810, and this output level in turn becomes an output level of redundancy select circuit 3. Thus, the output level of fuse program circuit 810 is at an L level when a fuse is not blown and at an H level when the fuse is blown.
In a normal mode, i.e., when redundant word line RWL is not in use (referred to as a "redundancy non-selected mode"), fuse F1 is connected. Thus, the potential of node N2 is at a ground level, and a signal of an L level is input to NAND circuit 5 in FIG. 17. As a result, decoder inactivation signal DA attains an H level, and the potential of redundant word line RWL remains inactive.
When redundant word line RWL is to be used (referred to as a "redundancy selected mode"), fuse F1 is blown. At power-on, the potential of node N2 starts to rise towards an H level because of capacitive coupling by the MOS capacitor C1. Further, the potential of node N2 reaches a complete H level by a positive feedback circuit consisting of transistor QN1 and inverter INV1.
Accordingly, in the redundancy non-selected mode, the output of redundancy select circuit 3 attains an L level; whereas, in the redundancy selected mode, it attains an H level.
FIG. 19 is a circuit diagram illustrating a detailed configuration of replacement address program circuit 4. An address setting circuit 40 includes a fuse F11, a MOS capacitor C11, an N channel MOS transistor QN11 and an inverter INV11. An address setting circuit 50 includes a fuse F12, a MOS capacitor C12, an N channel MOS transistor QN12 and an inverter INV12. The configuration and operation of each of address setting circuits 40 and 50 are similar to those of fuse program circuit 810 included in redundancy select circuit 3 shown in FIG. 18.
Thus, the potential at node N21 of address setting circuit 40 attains an L level when fuse F11 is connected and an H level when fuse F11 is blown. Similarly, the potential at node N22 of address setting circuit 50 is at an L level when fuse F12 is connected and at an H level when fuse F12 is blown.
Between an input terminal I1 and an output terminal O1 are connected P channel transistors 61, 62 and N channel transistors 71, 72. Similarly, P channel transistors 63, 64 and N channel transistors 73, 74 are connected between an input terminal I2 and output terminal O1; P channel transistors 65, 66 and N channel transistors 75, 76, between an input terminal I3 and output terminal O1; and P channel transistors 67, 68 and N channel transistors 77, 78, between an input terminal I4 and output terminal O1.
The gate electrodes of transistors 61, 73, 65, 77 are connected to node N21 of address setting circuit 40. The gate electrodes of transistors 71, 63, 75, 67 are connected to node N1 of address setting circuit 40. The gate electrodes of transistors 62, 64, 76, 78 are connected to node N22 of address setting circuit 50. And the gate electrodes of transistors 72, 74, 66, 68 are connected to node N12 of address setting circuit 50.
Pre-decode signals, obtained by pre-decoding X address signals XA, are programmed in replacement address program circuit 4 shown in FIG. 19. The way of programming in program circuit 4 will now be described.
First, pre-decode signals X0.multidot.X1, X0.multidot./X1, /X0.multidot.X1, /X0.multidot./X1 are defined as follows:
If X0=H level and X1=H level, then X0.multidot.X1=H level; PA1 If X0=H level and X1=L level, then X0.multidot./X1=H level; PA1 If X0=L level and X1=H level, then /X0.multidot.X1=H level; and PA1 If X0=L level and X1=L level, then /X0.multidot./X1=H level.
Under the conditions other than the above, pre-decode signals X0.multidot.X1, X0.multidot./X1, /X0.multidot.X1 and /X0.multidot./X1 each attain an L level.
Here, assume that pre-decode signal X0.multidot.X1 is applied to input terminal I1, pre-decode signal X0.multidot./X1 to input terminal I2, pre-decode signal /X0.multidot.X1 to input terminal I3, and pre-decode signal /X0.multidot./X1 to input terminal I4.
When fuses F11, F12 are both connected, only input terminal I1 is connected to output terminal O1, and accordingly, pre-decode signal X0.multidot.X1 appears at output terminal O1. Thus, the output at the time when X0=H level and X1=H level becomes an H level, and at this time, redundant word line RWL is selected. This means that an address of X0=X1=H level has been programmed to replacement address program circuit 4 by fuses F11 and F12.
When fuse F11 is blown or disconnected and fuse F12 is connected, pre-decode signal X0.multidot./X1 appears at output terminal O1. Thus, an address of X0=H level and X1=L level is programmed. When fuse F11 is connected and fuse F12 is disconnected, pre-decode signal /X0.multidot.X1 appears at output terminal O1. Thus, an address of X0=L level and X1=H level is programmed. When fuses F11 and F12 are both blown, pre-decode signal /X0.multidot./X1 appears at output terminal O1. Thus, an address of X0=X1=L level is programmed.
Replacement address program circuit 4 shown in FIG. 19 is provided with four pre-decode signals X0.multidot.X1, X0.multidot./X1, /X0.multidot.X1 and /X0.multidot./X1 obtained by pre-decoding two X address signals X0 and X1. Since there are normally four or more X address signals, a plurality of circuits each as shown in FIG. 19 are provided, with their outputs being input into NAND circuit 5 shown in FIG. 17.
With the configuration as described above, information as to whether the redundancy replacement should be conducted and an address where such redundancy replacement is to be conducted are recorded in a non-volatile manner, according to the connected/disconnected patterns of fuse elements.
It should be understood, however, that the configuration of fuse program circuit is not limited to that shown in FIG. 18.
FIG. 20 is a circuit diagram illustrating a configuration of another conventional fuse program circuit 800.
Fuse program circuit 800 includes: a capacitor C1 provided between a node N1 and a power supply potential Vcc; a fuse element F1 provided between node N1 and a ground potential GND; a P channel MOS transistor QP1 provided between node N1 and a power supply potential Vcc; and an inverter INV1 that receives and inverts the potential of node N1 and supplies its output to a gate of the transistor QP1.
Transistor QP1 and inverter INV1 constitute a half latch.
The output of inverter INV1 is applied to a node N2, which becomes an output potential of fuse program circuit 800. The potential level of node N2 is at an H level when the fuse is not blown, and becomes an L level when the fuse is blown.
Thus, fuse program circuit 800 shown in FIG. 20 has fundamentally the same configuration as fuse program circuit 810 shown in FIG. 18, except that polarities of the transistors are complementary to each other and, in response, the circuit configuration has been modified.
Now, disadvantages in the operations of these circuits will be explained, first as to the circuit shown in FIG. 20.
In general, fuse element F1 of FIG. 20 is made of polycrystalline silicon (polysilicon) or metal interconnection.
Fuse element F1 is normally disconnected as follows. Laser light is illuminated onto fuse element F1 to locally raise the temperature of the fuse, thereby causing fuse element F1 itself to evaporate.
A resistance of fuse element F1 before laser illumination is at most 10 K.OMEGA., although it varies dependent on the material being used.
Raising the resistance of fuse element F1 by laser illumination to an open state, i.e., at least 1G.OMEGA., corresponds to blowing of the fuse. Fuse program circuit 800 serves to recognize such a large change in resistance of the fuse.
There are some cases where the fuse material is not completely evaporated by laser illumination, for example, due to displacement of focus of laser light, variation in thickness of an insulating film deposited on the fuse, or subtle misalignment of the location to be illuminated, which causes a small portion of the fuse material to remain. In this case, fuse element F1 does not acquire a completely open state even after the laser illumination, with a high-resistance component being left. Hereinafter, such a remaining portion is called a "blown fuse remainder".
The structure of fuse element and disadvantages at the time of laser illumination are disclosed, for example, in Japanese Patent Laying-Open No. 10-340956 and Japanese Patent Laying-Open No. 11-17010.
At the time of mass production, there are cases where it is difficult to stabilize the high-resistance component due to the blown fuse remainder constantly at a level at least 10 M.OMEGA..
Fuse program circuit 800 shown in FIG. 20 is designed in such a way that the output level becomes an H level when fuse element F1 is not blown and an L level when fuse element F1 is blown.
Hereinafter, the case where there exists a high-resistance component of about 10 M.OMEGA. as the remainder of blown fuse element F1 will be considered.
Here, assume that power supply potential Vcc rises very slowly after power-on. In this case, capacitor C1 may not work effectively to set node N1 to an H level, and thus, the level of node N1 may be an L level even if the fuse is blown. In such a case, the output level of fuse program circuit 800 attains an H level, which leads to a malfunction.
Further, when the high-resistance component of about 10 M.OMEGA. exists, even if the level of node N1 becomes an H level and the output level of fuse program circuit 800 attains an L level assuring a normal operation, there may arise another problem that a stand-by current above a standard level flows.
More specifically, a leakage path for the current may be created through transistor QP1 connected to node N1, via the high resistance of the blown fuse remainder, towards ground potential GND. If power supply potential Vcc=3V, for example, the current value due to such a leakage path becomes I=V/R=3V/10M.OMEGA.=0.3 .mu.A.
In recent years, a requirement for the stand-by current for a static semiconductor memory device (SRAM), for example, has become extremely stringent. A standard value of such a stand-by current is, e.g., on the order of 1 .mu.A. Therefore, if an SRAM includes four blown fuses each having a high-resistance component left as the blown fuse remainder of about 10 M.OMEGA., the SRAM immediately becomes below standards, thereby decreasing the yield.
Similarly, fuse program circuit 810 shown in FIG. 18 is designed such that its output level becomes an L level when the fuse is not blown and an H level when the fuse is blown.
In this case, again, assume that there exists the blown fuse remainder. If power supply potential Vcc rises very slowly after power-on, as in the case of FIG. 20, capacitor C1 will not work effectively to cause node N1 to attain an L level. Accordingly, due to the high-resistance component as the blown fuse remainder, node N1 will attain an H level, the output level of fuse program circuit 810 will become an L level, thereby causing a malfunction.
Even in the case where node N1 becomes an L level after blowing the fuse, and even if the output level of fuse program circuit 810 becomes an H level and a normal operation is conducted, a stand-by current will inevitably flow from power supply potential Vcc via the high resistance of the blown fuse remainder towards transistor QN1. This again decreases the yield.